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LOW SKEW, PCI-X 1-TO-4 FANOUT BUFFER
ICS830584I
GENERAL DESCRIPTION
The ICS830584I is a low skew, general purpose IC S PCI-X 1-to-4 Fanout Buffer and a member of the HiPerClockSTM HiPerClockSTM family of High Performance Clock Solutions from IDT. Guaranteed output and partto-part skew characteristics make the ICS830584I ideal for those clock distribution applications demanding well defined performance and repeatablility. The ICS830584I is designed and characterized from -40C to 85C for industrial applications and is packaged in an 8 TSSOP package.
FEATURES
* General purpose and PCI-X 1:4 clock buffer * Four single-ended LVCMOS/LVTTL clock outputs * One single-ended LVCMOS/LVTTL clock input * Maximum output frequency: 140MHz
* Output enable control (outputs disabled in logic low state) * * Output skew: 100ps (maximum) Part-to-part skew: 400ps (maximum)
* Additive phase jitter, RMS: 0.15ps (typical) * Space-saving 8 lead TSSOP package * Full 3.3V operating supply mode * -40C to 85C ambient operating temperature
* Available in lead-free (RoHS 6) packages
BLOCK DIAGRAM
Q0
PIN ASSIGNMENT
CLKIN OE Q0 GND 1 2 3 4 8 7 6 5 Q3 Q2 VDD Q1
Q1 CLKIN Q2
ICS830584I
8-Lead TSSOP 4.40mm x 3.0mm x 0.925mm package body G Package Top View
Q3 OE
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TABLE 1. PIN DESCRIPTIONS
Number 1 2 3, 5, 7. 8 4 6 Name CLKIN OE Q0, Q1, Q2, Q3 GND VDD Input Input Output Power Power Type Description Single-ended clock input reference signal. LVCMOS/LVTTL interface levels. Output enable control input pin. See Table 3, Function Table. LVCMOS / LVTTL interface levels. Single-ended clock outputs. LVCMOS/LVTTL interface levels. Power supply ground. Positive supply pin.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN ROUT Parameter Input Capacitance Output Impedance Test Conditions Minimum Typical 4 15 Maximum Units pF
TABLE 3. FUNCTION TABLE
Inputs OE 0 0 1 1 CLKIN 0 1 0 1 Outputs Q0:Q3 0 0 0 1
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ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD Inputs, VI Outputs, VO Storage Temperature, TSTG 4.6V -0.5V to VDD + 0.5 V -0.5V to VDD + 0.5V -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause per manent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Package Thermal Impedance, JA 121.5C/W (0 mps)
TABLE 4A. RECOMMENDED OPERATING CONDITIONS, VDD = 3.3V 0.3V, TA = -40C TO 85C
Symbol VDD VIH VIL VI IOH IOL TA Parameter Positive Supply Voltage High Level Input Voltage Low Level Input Voltage Input Voltage High-Level Output Current Low-Level Output Current Operating Free-Air Temperature -40 0 Test Conditions Minimum 3.0 0.7*VDD 0.3*VDD VDD -24 24 85 Typical 3.3 Maximum 3.6 Units V V V V mA mA C
TABLE 4B. DC CHARACTERISTICS, VDD = 3.3V 0.3V, TA = -40C TO 85C
Symbol VIK VOH Parameter Input Voltage Output High Voltage Test Conditions II = -18mA IOH = -1mA IOH = -24mA IOH = -12mA IOL = 1mA VOL Output Low Voltage IOL = 24mA IOL = 12mA IOH IOL II IDD Ci Co
Minimum VDD - 0.2 2 2.4
Typical
Maximum -1.2
Units V V V V
0.2 0.8 0.55 -50 -5 5 60 70 150 37 3 3.2
V V V mA mA mA mA A mA pF pF
Output High Current Output Low Current Input Current Dynamic Current Input Capacitance Output Capacitance
VO = 1V VO = 1.65V VO = 2V VO = 1.65V VI = 0V or VDD f = 67MHz VI = 0V or VDD VI = 0V or VDD
All typical values are at respective nominal VDD and 25C.
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TABLE 5. AC CHARACTERISTICS, VDD = 3.3V 0.3V, TA = -40C TO 85C
Symbol Parameter fclk tpLH tpHL Clock Frequency; NOTE 1 Propagation Delay, Low to High; NOTE 2 Propagation Delay, High to Low; NOTE 2 Output Skew; NOTE 3, 4 Pulse Skew Process Skew Par t-to-Par t Skew; NOTE 4, 5 Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter section CLK High Time CLK Low Time Output Rise Slew Rate 140MHz, Integration Range: 10kHz - 20MHz 66MHz 140MHz 66MHz 140MHz 0.2VDD to 0.6VDD 140MHz 200 250 0.15 6 3 6 3 1.5 2.7 4 Test Conditions Minimum 0 1.8 1.8 2.5 2.4 50 Typical Maximum 140 3 3 100 170 300 400 Units MHz ns ns ps ps ps ps ps ns ns ns ns V/ns
t sk(o) t sk(p) t sk(pr) t sk(pp) tjit
Thigh Tlow tR
Output Fall Slew Rate 0.6VDD to 0.2VDD 1.5 2.7 4 V/ns tF All typical values are at respective nominal VDD. This symbol is according to PCI-X terminology. NOTE 1: Switching characteristics over recommended ranges of supply voltages and operating free-air temperature, CL = 10pF, VDD = 3.3V 0.3V. NOTE 2: Measured from VDD/2 of the input to VDD/2 of the output. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDD/2. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. NOTE 5: Defined as skew between outputs on different devices operating a the same supply voltages and with equal load conditions. Using the same type of input on each device, the output is measured at VDD/2.
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ADDITIVE PHASE JITTER
The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels (dBm) or a ratio of the power in the 1Hz band to the power in the fundamental. When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot.
Input/Output Additive Phase Jitter at 140MHz (12kHz - 20MHz) = 0.15ps typical
SSB PHASE NOISE dBc/HZ
OFFSET FROM CARRIER FREQUENCY (HZ)
As with most timing specifications, phase noise measurements has issues relating to the limitations of the equipment. Often the noise floor of the equipment is higher than the noise floor of the
device. This is illustrated above. The device meets the noise floor of what is shown, but can actually be lower. The phase noise is dependent on the input source and measurement equipment.
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PARAMETER MEASUREMENT INFORMATION
VDD
V
140 Yn
DD
Qx
2
V
10pF 140
DD
Qy
2 tsk(o)
3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT
OUTPUT SKEW
Part 1 Qx
V
VDD
VDD 2 VDD VDD 2 tpHL
DD
2
CLKIN
2
Part 2 Qy
V
Q0:Q3
DD
2 tpLH
2 tsk(pp)
PART-TO-PART SKEW
V
PROPAGATION DELAY
DD
Q0:Q3
t PW
t
2
PERIOD
tcyc thigh
odc =
t PW t PERIOD
x 100%
VIH(min) Vtest VIL(max)
0.6VDD tlow
0.2VDD
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
0.4VDD
Peak-to-Peak (min)
0.6VDD
0.6VDD
Parameter VIH(min) VIL(max) Vtest
Value 0.5VDD 0.35VDD 0.4VDD
Unit V V V
VR
0.2VDD
VF
0.2VDD
Q0:Q3
tR
tF
NOTE: All parameters are according to PCI-X 1.0 specifications
OUTPUT RISE/FALL SLEW RATES
CLOCK WAVEFORM
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PARAMETER MEASUREMENT INFORMATION, CONTINUED
Supply Current vs Frequency
35
VDD=3.6V TA=85 C
30
o
25
IDD - Supply Current - mA
20
15
10
5
0 0 20 40 60 80 f - Frequency - MHz 100 120 140 160
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APPLICATION INFORMATION
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS INPUTS: OUTPUTS:
OE INPUT The OE pin must be tied either HIGH or LOW. Do not leave floating. LVCMOS OUTPUTS All unused LVCMOS outputs can be left floating. We recommend that there is no trace attached.
RELIABILITY INFORMATION
TABLE 6. JAVS. AIR FLOW TABLE
FOR
8 LEAD TSSOP
JA by Velocity (Meters per Second)
0
Multi-Layer PCB, JEDEC Standard Test Boards 121.5C/W
1
117.3C/W
2.5
115.3C/W
TRANSISTOR COUNT
The transistor count for ICS830584I is: 307
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PACKAGE OUTLINE - G SUFFIX FOR 8 LEAD TSSOP
TABLE 7. PACKAGE DIMENSIONS
SYMBOL N A A1 A2 b c D E E1 e L aaa 0.45 0 -4.30 0.65 BASIC 0.75 8 0.10 -0.05 0.80 0.19 0.09 2.90 6.40 BASIC 4.50 Millimeters Minimum 8 1.20 0.15 1.05 0.30 0.20 3.10 Maximum
Reference Document: JEDEC Publication 95, MO-153
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TABLE 8. ORDERING INFORMATION
Part/Order Number Marking Package Shipping Packaging Temperature 830584AGILF 84AIL 8 lead "Lead-Free" TSSOP tube -40C to 85C 84AIL 8 lead "Lead-Free" TSSOP 2500 tape & reel -40C to 85C 830584AGILFT NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
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REVISION HISTORY SHEET Rev B Table T4B Page 3 Description of Change DC Characteristics Table - corrected Input Current typo from 5A max. to 150A max. Date 3/18/08
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Europe
IDT Europe, Limited 321 Kingston Road Leatherhead, Surrey KT22 7TU England +44 (0) 1372 363 339 +44 (0) 1372 378851 (fax)
(c) 2008 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA

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